Nado15

iEDA

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

tiny-asic-1_58bit-matrix-mul

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

FreePDK3

electrum

Electrum Bitcoin Wallet

RTL_synthesis_using_sky130

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

z80-verilog

A Thoroughly Tested Verilog Implementation of a Z80 Compatible Processor Architecture

8bit-computer

A simple 8-bit computer build in Verilog.

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

gb-research

Game Boy hardware research

OneClick-macOS-Simple-KVM

Tools to set up a easy, quick macOS VM in QEMU, accelerated by KVM. Works on Linux AND Windows.

fpu

IEEE 754 floating point library in system-verilog and vhdl

rvv-intrinsic-doc

openc910

OpenXuantie - OpenC910 Core

MSP430-CORDIC-sine-cosine

emulsiV

A visual simulator for teaching computer architecture using the RISC-V instruction set

RISC-V-Vector

Vector processor for RISC-V vector ISA

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-isa-sim

Spike, a RISC-V ISA Simulator

Rudi-RV32I

A rudimental RISCV CPU supporting RV32I instructions, in VHDL

cozy

🎧 Listen to audio books 📚 on Linux

eclipse-plugins

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

simple_pic

Simple Programmable Interrupt Controller

Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

riscv-gcc

nerv

Naive Educational RISC-V -- A simple single-stage RV32I processor

aoc2020

advent of code 2020

riscv-isa-manual

RISC-V Instruction Set Manual