Low overhead microbenchmarks for NVIDIA GPGPUs Instructions latencies (PTX and SASS) and the access cycles of the various memory hierarchies found in different NVIDIA GPU architectures
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[HPEC ’19] Low Overhead Instruction Latency Characterization for NVIDIA GPGPUs
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If you find this code useful in your research, please consider citing as:
@INPROCEEDINGS{Arafa2020HPEC,
author={Y. {Arafa} and A. A. {Badawy} and G. {Chennupati} and N. {Santhi} and S. {Eidenbenz}},
booktitle={2019 IEEE High Performance Extreme Computing Conference (HPEC)},
title={Low Overhead Instruction Latency Characterization for NVIDIA GPGPUs},
year={2019},
pages={1-8},
doi={10.1109/HPEC.2019.8916466}}
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- Code Name: Performance Prediction Toolkit, C17098
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