Navinkumar K's repositories
riscv-proc
32-bit 5-Stage Pipelined RISC V RV32I Core
rtl-sky130-ws
This is a documentation of the work done as part of the 5 - day RTL Design Workshop using Verilog with SKY130 Technology
osfpga-fda
This repository contains the work done as part of the 5 Workshop on FPGA - Fabric, Design and Architecture sponsored by the OSFPGA Foundation
cmos-amplifier
Simulation of CMOS Amplifier with current mirror biasing and PMOS Active load
mixed-riscv-soc
This repository contains the work as part of the 1 day workshop on Mixed-Signal RISC-V based SoC on FPGA sponsored by the OSFPGA Foundation
rad-2-booth
This repository contains the verilog design of a radix to booth's algorithm
rev-cla-16
This documentation contains the implementation of a 16 - bit reversible logic carry look ahead adder
riscv-myth-ws
This repository contains the work done as part of the 5 Day OSFPGA RISC - V Workshop
trans-full-adder
1 - bit Full Adder implementation using Transmission Gate Logic and Conventional Inverter.