MounishT / workshop-DE

workshop-DE

DEVELOPED BY:T MOUNISH

REGISTER NO: 212223240098

VERILOG CODE:

module workshop (
    input [3:0] A,
    input [3:0] B,
    input Cin,
    output [3:0] Sum,
    output Cout
);

assign {Cout, Sum} = A + B + Cin;

endmodule

RTL VIEW:

RUN TIME SIMULATION:

RESULT:

Thus, Successfully executed the Simulation in verilog HDL for 4 bit Ripple Carry Adder using Quartus II.