MineFujiko

my-vscode-verilog-ext

MineFujiko.github.io

chisel

A fast TCP/UDP tunnel over HTTP

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Digital-IDE

在vscode上的数字设计开发插件

dma_ip_drivers

Xilinx QDMA IP Drivers

e200_opensource

The Ultra-Low Power RISC Core

hbird-e-sdk

Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/

hugotalks

icestudio

:snowflake: Visual editor for open FPGA boards

jesd204b

JESD204B core for Migen/MiSoC

latex_module

my_config_files

my_hdl

OFDM

A MATLAB program to help understand OFDM.

openwifi

open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

pasteex-mode

An Emacs extension that save clipboard image to disk file, and insert file link to current point.

pcileech-fpga

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

petalinux

pyda-2e-zh

:book: [译] 利用 Python 进行数据分析 · 第 2 版

pyfda

Python Filter Design Analysis Tool

pysvinst

Python library for parsing module definitions and instantiations from SystemVerilog files

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-tests

u-boot-socfpga

U-Boot development repository for socfpg

verilog-axi

Verilog AXI components for FPGA implementation

verilog-pcie

Verilog PCI express components

Verilog-Practice

HDLBits website practices & solutions

vimcdoc

Vim 中文文档计划

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!