MeDove's repositories
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language:SystemVerilogNOASSERTION000
MIT000
dsi-shield
Arduino MIPI DSI Shield
Language:VHDLLGPL-3.0000
Language:HTML000
hexo-theme-zhaoo
🐳 A simple theme for Hexo
Language:EJSMIT000
i3c-slave-design
MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
Language:VerilogNOASSERTION000
iverilog
Icarus Verilog
Language:C++GPL-2.0000
Language:HTML000
verilog-axis
Verilog AXI stream components for FPGA implementation
Language:PythonMIT000
verilog-ethernet
Verilog Ethernet components for FPGA implementation
Language:VerilogMIT000
verilog-i2c
Verilog I2C interface for FPGA implementation
Language:VerilogMIT000
verilog-pcie
Verilog PCI express components
Language:VerilogMIT000
verilog-uart
Verilog UART
Language:VerilogMIT000
vscode
Visual Studio Code
MIT000
wbuart32
A simple, basic, formally verified UART controller
GPL-3.0000