Master-ic

master99's repositories

2023-FPGA-summer-camp

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学习Cache的开源项目备份

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Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

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A minimal GPU design in Verilog to learn how GPUs work from the ground up

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**科学技术大学课程资源

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一个开放的节点库，为了自由的隐私

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Verilog to Routing -- Open Source CAD Flow for FPGA Research

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一部の不正な王様には向きません

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ysyx22060028

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