Martoni / chisverilogutils

Quick and Dirty python scripts that modify verilog modules generated by Chisel

Chisel, Cocotb, smtbmc toolkit

Some usefull python scripts to works with Chisel, Verilog, cocotb, smtbmc, ...

Each following software are standalone python package. To install it just go to directory and do :

$ python -m pip install -e .

Executable have the name of chapter software.

cocotbify

Quick and Dirty python script to add timescale and vcd in verilog module generated by chisel backend

smtbmcify

Inject somes SystemVerilog assert/assume under verilog chisel generated module.

cocotbgen

Generate cocotb testbench files for a Chisel Module specified in argument

chiselformalcleaner

Delete useless formal code generated by chisel-formal trait in pure verilog file