A System Verilog Design of the Shift-sub Modular Multiplier Algorithm
This repository introduces a Shift-Sub Modular Multiplication (SSMM) algorithm SSMMul(a, b, m) to calculate z = ab mod m that uses only addition, subtraction, and shift calculations for a, b < m
- At the beginning, let product z = 0.
- We check the least significant bit of multiplier b.
- If it is a 1, we add multiplicand a to product z.
- Then we shift a to the left and b to the right by one bit, respectively.
- Because a < m, a ← 2a < 2m
- Similarly, z = 0 at the beginning or z = a after the first adding a to z, then we have z ← z + a ≤ 2a < 2m.
- After the addition and shift, we perform the following operations: If z > m, z ← z − m; if a > m, a ← a − m.
- Such operations ensure z < m and a < m
- The computational complexity of the Shift-Sub Modualr Multiplier is the same as that of Motgomery Modular Multiplier
- The advantage of the Shift-Sub Modular Multiplier is that it does not require any domain transformation which was done in the montgomery algorithms
- The correctness of the SSMM algorithm is based on the following fact: Because we are calculating z = ab mod m, we can add/subtract multiples of m to/from z.
- The Implemented algorithm computes the modular multiplication of a*b mod(m) up to 256 bits
- Most of computations are done within about 5 to 10 clock cycles