MahmouodMagdi / 64-bit-Single-Cycle-RISC-V-Core

Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA

64-bit-Single-Cycle-RISC-V-Core

Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA

Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA

MIT License

Language:SystemVerilog 100.0%