Lyther / Minisys

Using Verilog to design a CPU with MIPS32 RISC

#version 0.0.1

1. The initial version of CPU design, current only file system is here.
2. At least you can add this into your vivado.

#version 0.1.1

1. Finished clock design and simulation: after 620ns then the clock signal divides correct.
2. All the modules are created.

#version 0.2.0

1. Basic functions are finished, and I'm working on debugging.
2. Instructions cannot be read in.

#version 0.3.0

1. Fix some code problems in previous version.
2. Over fix leads to PC doesn't increase.

#version 1.0.0

1. Well designed version that can work well in simulation.
2. Tesing on minisys board.

#version 1.0.1

1. Cannot run implementation.
2. Finally give up.