Loester Franco's repositories
bashbrew
Canonical build tool for the official images
carbon-lang
Carbon Language's main repository: documents, design, implementation, and related tools. (NOTE: Carbon Language is experimental; see README)
CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online workshop: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
docker-alpine-glibc
Minimal Alpine Linux Docker image with glibc
gdsfactory
Python package to generate GDS layouts.
globalfoundries-pdk-libs-gf180mcu_fd_bd_sram
SRAM build space for the GF180MCU provided by GlobalFoundries.
globalfoundries-pdk-libs-gf180mcu_osu_sc
Digital standard cells for GF180MCU provided by Oklahoma State University.
globalfoundries-pdks
Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
hyperv-fix-for-devs
Installation Script for the Hyper-V / WSL2 Network Fix for Linux Developers
PowerDNS-Admin
A PowerDNS web interface with advanced features
Robot-Framework-Mainframe-3270-Library
Altran developed and open source a test library for Robot Framework to enable to create automated test scripts to test IBM Mainframe 3270.
scikit-learn
scikit-learn: machine learning in Python
skywater-pdk-ip-sky90fd_fd_ip_sram
SRAM build space for SKY90FD provided by SkyWater.
skywater-pdk-libs-sky90fd_fd_io
IO and periphery cells for SKY90FD provided by SkyWater.
skywater-pdk-libs-sky90fd_fd_pr
Primitives for SKY90FD provided by SkyWater.
skywater-pdk-libs-sky90fd_fd_sc
Standard cells for SKY90FD provided by SkyWater.
skywater-pdk-libs-sky90fd_osu_sc
Standard cells for SKY90FD provided by Oklahoma State University.
skywater-pdk-sky130-raw-data
Raw data collected about the SKY130 process technology.
skywater130
skywater 130nm pdk
SystemVerilog_Design_Verification
Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog