This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 1440 LUT4s (180x CLBs) and 180 LUT5s (45x RegFiles) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
- Due to the issue of routing with the Openlane flow, this version was using Cadence Innovus for physical implementations.
- The Yosys was used to synthesize the design RTL. An example can be found here
- The Liberty files (.lib) and GDS files for standard cell library need to be copied from Sky130 PDK to TIMING and GDS folder respectively if using the impl_commands.tcl
UoM_eFPGA
├── common
│ ├── GDS
│ │ ├── CPU_IO.gds
│ │ ├── eFPGA_top.gds
│ │ ├── LUT4AB.gds
│ │ ├── N_term_single2.gds
│ │ ├── N_term_single.gds
│ │ ├── RegFile.gds
│ │ ├── sky130_ef_io.gds
│ │ ├── sky130_fd_io.gds
│ │ ├── sky130_fd_sc_hd.gds
│ │ ├── S_term_single2.gds
│ │ ├── S_term_single.gds
│ │ └── W_IO.gds
│ ├── LEFfile
│ │ ├── CPU_IO.lef
│ │ ├── eFPGA_top.lef
│ │ ├── LUT4AB.lef
│ │ ├── N_term_single2.lef
│ │ ├── N_term_single.lef
│ │ ├── RegFile.lef
│ │ ├── sky130_ef_io.lef
│ │ ├── sky130_fd_io.lef
│ │ ├── sky130_fd_sc_hd.lef
│ │ ├── sky130_fd_sc_hd.tlef
│ │ ├── S_term_single2.lef
│ │ ├── S_term_single.lef
│ │ └── W_IO.lef
│ ├── MAP
│ │ └── sky130_lefpin.map
│ ├── MMMC
│ │ ├── UoM_eFPGA_mmmc_TClib.view
│ │ └── UoM_eFPGA_mmmc.view
│ ├── SCRIPTS
│ │ ├── impl_commands.tcl
│ │ ├── stream_gds.tcl
│ │ └── write_leflib.tcl
│ ├── SDC
│ │ ├── pnr
│ │ │ ├── func.ideal.bc.tcl
│ │ │ ├── func.ideal.wc.tcl
│ │ │ └── func.prop.tcl
│ │ └── synthesis
│ │ └── eFPGA_top.sdc
│ ├── SRC
│ │ ├── UoM_eFPGA.io
│ │ └── UoM_eFPGA.v
│ └── TIMING
│ ├── CPU_IO.lib
│ ├── eFPGA_top.lib
│ ├── LUT4AB.lib
│ ├── N_term_single2.lib
│ ├── N_term_single.lib
│ ├── RegFile.lib
│ ├── sky130_fd_sc_hd__ff_n40C_1v95.lib
│ ├── sky130_fd_sc_hd__ss_100C_1v60.lib
│ ├── sky130_fd_sc_hd__tt_025C_1v80.lib
│ ├── S_term_single2.lib
│ ├── S_term_single.lib
│ └── W_IO.lib
├── OUTPUT
└── SAVED- Update CLB, RegFile blocks
- Provide DSP, BRAM blocks
- Provide custom cells (e.g., multiplexers)
- Implement the fabric using the Openlane flow