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KylinChang / Arch

Project for the course Computer Architecture. It aims to develop a pipeline MIPS CPU with cache in FPGA step by step.

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#Arch

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Project for the course Computer Architecture. It aims to develop a pipeline MIPS CPU with cache in FPGA step by step.

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Language:VHDL 30.7%Language:HTML 23.9%Language:Tcl 13.9%Language:Verilog 13.5%Language:Shell 9.2%Language:Batchfile 4.1%Language:Stata 4.0%Language:SystemVerilog 0.6%Language:C++ 0.1%Language:Assembly 0.0%