Kreijstal's repositories
AND-gate-cosim-madness
AND Gate Cosimulation Examples: Open-source hardware simulation playground using Verilog, VHDL, C/C++, Python. Explore Verilator, GHDL, Icarus Verilog, MyHDL, and more. Learn digital design and HW/SW co-simulation through practical, comparative examples. Ideal for students and curious engineers.
binary-parser
Blazing-fast declarative binary parser and encoder builder for node.js
cetz
CeTZ: ein Typst Zeichenpaket - A library for drawing stuff with Typst.
install-verilator-action
Install Verilator for use in a Github Action workflow
Jasm2
Post modern age integration focused jvm bytecode assembler
js-interpreter2
NPM package for Neil Fraser's amazing JS-Interpreter
lispc-embedded
A simple Lisp interpreter in C attempting to make it work for barebones C
MINGW-packages
Package scripts for MinGW-w64 targets to build under MSYS2.
mobydick
GTK+ app to download music from Funkwhale
mrustc
Alternative rust compiler (re-implementation)
MSYS2-packages
Package scripts for MSYS2.
napi-rs
A framework for building compiled Node.js add-ons in Rust via Node-API
py4cytoscape
Python library for calling Cytoscape Automation via CyREST
pydesignflow
Micro-Framework for FPGA / VLSI Design Flow in Python
python-igraph
Python interface for igraph
rolldown
Fast Rust bundler for JavaScript/TypeScript with Rollup-compatible API.
sentencepiece
Unsupervised text tokenizer for Neural Network-based text generation.
tree-sitter-language-pack
A tree-sitter language pack
upterm
Instant Terminal Sharing
verilator-unisims
This is mainly a simulation library of xilinx primitives that are verilator compatible.