KirollosSamy / Five-stages-pipeline-processor

This is an implementation of a five stages pipeline processor using verilog

This is a 32-bit 5 stage pipelined processor using Harvard Architecture

Instruction Fetch (IF)	Instruction Decode (ID)	Execute (Ex)	Memory (Mem)	Write Back (WB)

This is an implementation of a five stages pipeline processor using verilog

MIT License

Language:Verilog 93.1%Language:Python 6.8%Language:Stata 0.1%