Zhenghao He's repositories
open_usb1.1_host
from opencore, Including the controller and phy
antsdr-fw
ANTSDR Firmware
BibiGPT-v1
BibiGPT v1 · one-Click AI Summary for Audio/Video & Chat with Learning Content: Bilibili | YouTube | Tweet丨TikTok丨Dropbox丨Google Drive丨Local files | Websites丨Podcasts | Meetings | Lectures, etc. 音视频内容 AI 一键总结 & 对话：哔哩哔哩丨YouTube丨推特丨小红书丨抖音丨快手丨百度网盘丨阿里云盘丨网页丨播客丨会议丨本地文件等 (原 BiliGPT 省流神器 & AI课代表)
ChatGPT-Next-Web
A well-designed cross-platform ChatGPT UI (Web / PWA / Linux / Win / MacOS). 一键拥有你自己的跨平台 ChatGPT 应用。
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
dma_ahb
AHB DMA 32 / 64 bits
dport
Displayport core for aijuboard
electrocardiogram
electrocardiogram
FPGA_DisplayPort
An implementation of DisplayPort protocol for FPGAs
hvp-language-support
This extension incorporates syntax highlighting for Hierarchical Verification Plan, Hierarchically describe a verification plan.
open_usb1.1_device
from opencore, Including the controller and phy
PeakRDL-pdf
Converts the SystemRDL data into pdf Register specification
KSP_zh
坎巴拉太空计划汉化项目
learning-journey
Chisel Learning Journey
Note_JD
Personal code notes about Data Structures and Algorithm
PYNQ-Classification
Python on Zynq FPGA for Convolutional Neural Networks
Python_JD
技术渣的学习之路
RegGenPerl
Generate Regisiter Verilog/Excel From a Description File
RISC-V-TLM
RISC-V SystemC-TLM simulator
Verilog_JD
Learning Verilog HDL
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
xdcom
This is a demo for still image compression application
xkISP
http://openasic.org/
yuu_register_productor
UVM register utility generation by inputting xls table
zhihu-terminal
终端版知乎客户端