ware's repositories
algorithm-visualizer
:fireworks:Interactive Online Platform that Visualizes Algorithms from Code
automatic-verilog
automatic-verilog based on vimscript
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Cores-VeeR-EL2
VeeR EL2 Core
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
dcf-gnu-toolchain
GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
Digital-Recognition-DTW_HMM_GMM
10 digits recognition system based on DTW, HMM and GMM
FineWeather
Version1.0
riscv-ci
Build scripts of ci.rvperf.org
cosim-arch-checker
Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
riscv-crypto
RISC-V cryptography extensions standardisation work.
riscv-isa-sim
Spike, a RISC-V ISA Simulator
RISCV-Measurement
This is a repo for recording and reporting RISCV platform's test and measurement continuously.
riscv-opcodes
RISC-V Opcodes
rv32_aes32sm4_verification
risc-v K extension verification
RV32_Crypto
v1.0
rv32_sha2sm3_verification
risc-v 32 K extension C verification code
XiangShan
Open-source high-performance RISC-V processor