Jayanth-sharma's repositories
Mixed-signal-Two-Step-Flash-ADC
This circuit is a part of Mixed Signal SOC design.
eSim-Cloud
A web-based system for designing and simulating electronic (eSim) and Arduino circuits.
-Dynamic-shift-Registers
This is a documentation of the steps involved in designing a 1-bit Dynamic Shift Register on the SYNOPSYS Custom Compiler - 32nm PDK
000
Barrel-Shifter-8-bit
RTL to GDS flow of a 8bit Barrel Shifter
Language:VerilogGPL-3.0000
000
FIFO-design
Designed 32-bit data Width Sync FIFO and Synchronizer.
Language:VerilogBSD-2-Clause000
Major-Project-PLL
Design of a Mixed Signal Fractional-N PLL
Apache-2.0000
msvsd2stepadc
VSD Mixed-signal PD Research Program
Language:VerilogApache-2.0000
msvsdspwm
VSD-Mixed-Signal-PD-Research
Language:Jupyter Notebook000
Language:Jupyter NotebookBSD-2-Clause000
Language:Verilog000
traffic-light-controller
A project to design FSMs based Traffic light controller with Variable Timers
Language:Verilog000
Language:C++Apache-2.0000