This Verilog module generates Pulse Width Modulation (PWM) signals using an input clock with a frequency of 12500Hz. The module includes two buttons for controlling the duty cycle of the PWM signal: one button for increasing the duty cycle and another for decreasing it. To prevent false triggering, the module also has debounce logic implemented for the buttons.
The module produces four output signals: inled, deled, led, and clock_1hz. The inled and deled signals are used to indicate when the duty cycle is at its maximum and minimum values, respectively. The led signal generates the actual PWM signal with a duty cycle controlled by the two buttons. Finally, the clock_1hz signal is a 1Hz clock signal generated from the input clock using a divisor of 12500.
The PWM signal is generated using an always block triggered by the input clock. The duty cycle is updated when the corresponding button is pressed, and the count for the PWM period is incremented at each clock cycle. The duty cycle value is used to control the led signal, which generates the PWM signal by toggling between 1 and 0 based on the count value. When the count reaches the maximum value, the PWM period is reset to zero.
The debounce logic for the buttons is implemented using two separate always blocks triggered by the input clock. The button count is incremented when the button is pressed, and it is reset to zero when the button is not pressed. Once the button count reaches a certain value, the corresponding debounced button signal is set to 1 to indicate a valid button press.
Overall, this Verilog module provides a simple and efficient way to generate PWM signals with adjustable duty cycles using buttons and debounce logic.
The verilog code was tested in a DE1-soc FPGA development board and found to be functional. The next step is to see if it works in the ASIC implementation.
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