Introspecting's repositories
introduction_to_ml_with_python
Notebooks and code for the book "Introduction to Machine Learning with Python"
finn
Dataflow compiler for QNN inference on FPGAs
NvdlaSmallTraceTest
NVDLA small版本的踪迹测试，用于在裸机环境下运行。
verilog-axi
Verilog AXI components for FPGA implementation
nvdla-parser
A NVDLA Loadable Parser.
yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
DepthwiseCONV-HLS
使用HLS设计一个可分卷积（High Level Synthesis）模块，以在FPGA上对其进行加速。
chisel-tutorial
chisel tutorial exercises and answers
sw
NVDLA SW
heterohalide
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
neuro-vectorizer
NeuroVectorizer is a framework that uses deep reinforcement learning (RL) to predict optimal vectorization compiler pragmas for for loops in C and C++ codes.
nvdla-workload
Base NVDLA Workload for FireMarshal
caffe
Caffe: a fast open framework for deep learning.
hw
RTL, Cmodel, and testbench for NVDLA
MTCNN_with_HLS_On_FPGA
MTCNN with convolution reprogramed in c
caffe-tensorflow
Caffe models in TensorFlow
CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
dnnweaver2
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
Zeus
NVDLA small config implementation on Zynq ZCU104 (evaluation)
vp
Virtual Platform for NVDLA
Halide-HLS
HLS branch of Halide
buildroot
Buildroot source code using to create rootfs for NVDLA image