tp3-team-7 created by GitHub Classroom TP3 - Electrónica III
There are only three folders with all project content that are
- doc: contains project tex files for each task
- data: contains project aditional resources (images, pdfs) files
- EJ1/verilog: contains the verilog codes for task 1a.
- EJ1/verilog_ejb: contains the verilog codes for task 1b
- EJ2/verilog: contains the verilog codes for task 2a.
- EJ2/verilog_ejb: contains the verilog codeds for task2b
- EJ3/verilog: contains the verilog codes for task 3a
- EJ3/verilog_ejb: contains the verilog codes for task 3b
Note: all other files are not the final project but were part of our process making the project.
Important:
- To compile the report run make on root directory, report.pdf file with project content will be produced.
- To compile the task 1/2/3 verilog plese open one of the three modules folders and run make. Executable will be made in bin folder. By running executable you'll get .vcd file that using gtkwave will show the output of verilog tests.