HydroRifle / HES

Table of Content

1. HES
   • Vivado - board definition files

HES

HES™ is a SoC/ASIC pre-silicon prototyping solution for hardware verification and software validation teams and the High Performance Computing (HPC) platform for algorithms acceleration. The boards are based on largest Virtex-7 and Virtex UltraScale FPGA and appear in single or multi-FPGA configurations and can be interconnected on a backplane board providing up to 663 Million ASIC gates.

Aldec provides the following list of boards:

• Virtex UltraScale+ Boards
  • HES-XCVU9P-QDR (Xilinx Virtex UltraScale+ XCVU9P FPGA)
  • HES-XCVU9P-ZU7EV (ZU7EV Zynq® UltraScale+™ MPSoC and a VU9P Virtex® UltraScale+™ FPGA)
• Virtex UltraScale Boards
  • HES-US-440 (Virtex UltraScale XCVU440)
  • HES-US-1320 (3x Virtex UltraScale XCVU440)
  • HES-US-2640 (6x Virtex UltraScale XCVU440)
• Virtex-7 Boards
  • HES7XV4000BP (Virtex-7 2000T)
  • HES7XV1380BP (Virtex-7 690T)
  • HES7XV12000BP (6x Virtex-7 2000T)

Link to the HES boards page

Vivado - board definition files

Vivado board definition files contain configuration of FPGAs available on the board to simplify using the Aldec HES board in Xilinx Vivado tool.

The board definition files for HES boards can be found in Vivado-board_files folder.

The board definition files are provided for the following Aldec HES boards:

• HES-XCVU9P-QDR (Xilinx Virtex UltraScale+ XCVU9P FPGA)
• HES-XCVU9P-ZU7EV (ZU7EV Zynq® UltraScale+™ MPSoC and a VU9P Virtex® UltraScale+™ FPGA)
• HES-US-440 (Virtex UltraScale XCVU440)