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WinDLX DLX-Pipeline Simulator
(c) Copyright 1992 by by TU Vienna, Inst. f�r Technische Informatik
DLX simulator (c) Copyright 1989 by Regents of the University of California

This README contains information for the first-time installation of WinDLX
as it is distributed on this diskette.


What is WinDLX?
---------------
WinDLX is a pipeline simulator for the DLX processor as described in

    D.A. Patterson / J.L. Hennessy: Computer Architecture -
                                    A Quantitative Approach
         Morgan Kaufmann Publishers, San Mateo, California

It is a MS-Windows based frontend for the text-only DLX simulator available
by the above authors.
After loading a symbolic DLX assembler code, most of the information relevant
to the CPU (pipeline, registers, I/O, memory, ...) can be viewed and modified
while executing the code step-by-step or continuously. WinDLX offers statistics
about pipeline behavior in time.
This program greatly helps people in understanding pipelining concepts as well
as other architectural specifics of RISC processors.


System prerequisites
--------------------
IBM personal computer or lookalike with DOS 3.3 or later and Microsoft
Windows 3.0 or newer.


Installation
------------
The file WINDLX_D.EXE on this diskette is a self-extracting archive.
To unpack it, follow these steps:

1.) create a directory "WINDLX" somewhere on your harddisk and make this
    directory your current.

2.) type in the following line:

		A:\WINDLX\WINDLX_D

    This will unpack the files in the archive and install them on the harddisk.

    The following files will be created:

       WINDLX.EXE -- the WinDLX executable
       WINDLX.HLP -- Windows helpfile
       *.S        -- sample assembler input files
       README     -- this file
           .....


3.) Install the program into the Program Manager and click on the symbol to
    start it. The help facility is very extensive and covers almost everything
    we could think of.


Feel free to create your own assembler files and experiment with different
CPU configurations.

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