Hussien Mostafa's repositories
adder_floatining_point_ieee754
adder uses ieee754 format written in System Verillog
Data-Analysis-Olympics
doing data analysis on data set 120-years-of-olympic-history-athletes-and-results in kaggle https://www.kaggle.com/hmselkholy/olympics-analysis
Awesome-CV
:page_facing_up: Awesome CV is LaTeX template for your outstanding job application
aesd-assignments
Public starter source code, scripts, and documentation for AESD assignments
aima-python
Python implementation of algorithms from Russell And Norvig's "Artificial Intelligence - A Modern Approach"
arch_lab09
single cycle mips implementation with systemverilog
digital-clock-with-AVR-atmega-16
digital clock made with ATmega16 using C language with eclipse IDE and proteus (interrupts for buttons + timer for calculting time + GPIO for displaying time on multiplixed 7-sgement)
Multimeter_AVR
multimeter with AVR subimted during Lab and Measurements ECE310 course
paymentApp1
FWD - professional embedded systems nano degree
pipline_mips
pipline mips processor with systemverilog
assignment-autotest
Auto test code for assignments, using the Unity automated test framework
Awesome-Embedded
A curated list of awesome embedded programming.
awesome-interview-questions
:octocat: A curated awesome list of lists of interview questions. Feel free to contribute! :mortar_board:
compilerbook-examples
Example code for compilers textbook.
evil__car
car self reporting for traffic violation
gym
A toolkit for developing and comparing reinforcement learning algorithms.
lowlevelprogramming-university
How to be low-level programmer
MIPS_verilog
MIPS(R,I,jump,bne,beq) implementation with verilog
RTOS-Excersies
exercises practiced during Development of Real-Time Systems course
Speech-Separation-Paper-Tutorial
A must-read paper for speech separation based on neural networks