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GhiathAjam / SPI_Interface

Serial Peripheral Interface WIth Verilog

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SPI_Interface

Serial Peripheral Interface WIth Verilog

CMP 1st Year 2nd Term Logic Design 2 Project

Modules

  1. Master
  2. Slave
  3. Integration of a Master with 3 Slaves in a Regular Multi-slave mode
  4. Self-Checking Testbenches for the Master, Slave and Integration

(Additional info in Project Description.pdf)

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Serial Peripheral Interface WIth Verilog

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Language:Verilog 100.0%