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Fredx77 / sdraproject

SDRA2020 Vivado design

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sdraproject

SDRA2020 Vivado design This repository contains a Xilinx Vivado project setting up a simple SDR TX path in IP integrator, that compiles and runs on an Ultra96V2 single board computer.

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SDRA2020 Vivado design

License:GNU General Public License v3.0

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Language:VHDL 36.7%Language:C 32.4%Language:Verilog 14.9%Language:Tcl 9.2%Language:SystemVerilog 2.6%Language:C++ 2.4%Language:V 0.4%Language:Objective-C 0.2%Language:HTML 0.2%Language:Makefile 0.2%Language:Assembly 0.2%Language:JavaScript 0.2%Language:Shell 0.1%Language:Stata 0.1%Language:Scala 0.1%Language:CartoCSS 0.0%Language:Forth 0.0%Language:Batchfile 0.0%Language:Pascal 0.0%Language:PureBasic 0.0%