This repository holds the Verilog code designed for the course Digital Logic and Verilog
Most of the code is not designed to run on any specific board, and are only proof of concept (meaning that there're no specific solutions to solve any timing issues, etc.). In the future I may modify the code and complete them. This is only the state of the code when I submitted them.
I used Vivado to develop and simulate these codes. The target board is not specific, but I used EGO-1 as an experiment.
The update logs of the codes will be here.
- There're currently no update of the codes.