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FerrisChi / minisys-3

A basic MIPS CPU built in 3 days.

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minisys-3

A basic MIPS CPU built in 3 days.

Due to time restraints, a single-cycle MIPS CPU with 31 instructions was built. Also, we tried multi-cycle MIPS CPU and haven't take it into fully implementation.

Thanks to the SEU course, we abandoned our thought of building with RISC-V instruction set. But it turned out that they've made more features than us, including interrupt, CPU pipeline and so on.

orgnization contains a assembler made by SEU professors.

softwares contains assemble software written by our mates and only made for MIPS.

ref contains a reference project.

[计算机系统综合设计]https://www.icourse163.org/course/SEU-1003566002

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A basic MIPS CPU built in 3 days.

License:MIT License

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Language:VHDL 53.3%Language:Verilog 34.4%Language:PureBasic 7.1%Language:C 1.8%Language:C++ 1.2%Language:Shell 1.1%Language:Tcl 0.3%Language:JavaScript 0.3%Language:HTML 0.3%Language:Stata 0.1%Language:Batchfile 0.0%Language:Forth 0.0%Language:Assembly 0.0%Language:Pascal 0.0%