Abdelrhman M.Fathy's repositories

Language:C++Stargazers:9Issues:1Issues:0
Language:CStargazers:4Issues:1Issues:0

Hosipatl-Simulator

This Project is All about Practicing Some Low level C Programing. Console Application To simulate Hospital Which Have Patients Users and Doctors Users

Language:CStargazers:2Issues:1Issues:0

CMP3060_ComputerGraphics_labs

Weekly Computer Graphics Trials Using OpenGL library

Language:C++Stargazers:1Issues:1Issues:0

Be-Hulk

web system to manage gym using php

Language:PHPStargazers:0Issues:0Issues:0

Captain-Hook

🤖 Captain Hook is a robot which makes food and drinks using a wide range of functionalities cooperating together by Arduino for the full cooking process.

Language:C++License:MITStargazers:0Issues:0Issues:0

Doodle-Search-Engine

A web search engine built in java to serve you browse and search the web content.

Language:JavaStargazers:0Issues:0Issues:0
Language:C++Stargazers:0Issues:0Issues:0

GiT_Problem_Solving

My Answers To Some Problems On Code Forces

Language:C++Stargazers:0Issues:0Issues:0

Logic-Circuit-Simulator-1

💥 we are required to implement a simple logic circuit designer/simulator. The implementation with c++ (OOP)

Language:CLicense:MITStargazers:0Issues:0Issues:0

MP-Processor-Game

🛰️ MP-Processor-Game is an assembly language project by console window for your application and text/graphics mode GUI. It is about connecting 2 PCs through a Simple network, using serial communication. Two functions are to be implemented: chatting, and a two players’ processor simulation game.

Language:AssemblyLicense:MITStargazers:0Issues:0Issues:0

Operating-System

it is a simulator to show the function of the scheduler of the operating system, it schedules with many different algorithms keeping in mind the memory capacity

Language:CStargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

Serial-Peripheral-Interface

📡 In this project, we only focus on the Multi-Slave Regular Mode. We design and implement the following components of the SPI modules using Verilog such that they match the requirements of the development testbench and match the SPI specifications (Master - Slave - Self-Checking Testbenches for the Master and Slave)

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

Testing

This Repo is only For Testing Team Members

Stargazers:0Issues:0Issues:0