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EtnasSoft / AVR_ASSEMBLY_INSTRUCTION_SET

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Mnemonic Operands Description Operation Flags #ClocksAVRe #ClocksAVRxm #ClocksAVRxt #ClocksAVRrc
ADC Rd, Rr Add with Carry Rd ? Rd + Rr + C Z,C,N,V,S,H 1 1 1 1
ADD Rd, Rr Add without Carry Rd ? Rd + Rr Z,C,N,V,S,H 1 1 1 1
ADIW Rd, K Add Immediate to Word R[d + 1]:Rd ? R[d + 1]:Rd + K Z,C,N,V,S 2 2 2 N/A
AND Rd, Rr Logical AND Rd ? Rd ? Rr Z,N,V,S 1 1 1 1
ANDI Rd, K Logical AND withImmediate Rd ? Rd ? K Z,N,V,S 1 1 1 1
ASR Rd Arithmetic Shift Right CRd(n)Rd(7)? ? ?Rd(0)Rd(n+1), n=0..6Rd(7) Z,C,N,V 1 1 1 1
BCLR s Flag Clear SREG(s) ? 0 SREG(s) 1 1 1 1
BLD Rd, b Bit load from T to Register Rd(b) ? T None 1 1 1 1
BRBC s, k Branch if Status Flag Cleared if (SREG(s) == 0) thenPC? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRBS s, k Branch if Status Flag Set if (SREG(s) == 1) thenPC? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRCC k Branch if Carry Cleared if (C == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRCS k Branch if Carry Set if (C == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BREAK Break See the debug interface description None 1 1 1 1
BREQ k Branch if Equal if (Z == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRGE k Branch if Greater or Equal,Signed if (S == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 /2
BRHC k Branch if Half Carry Flag Cleared if (H == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRHS k Branch if Half Carry Flag Set if (H == 1) then PC ? PC + k + 1 None 1 / 2 1 /2 1 / 2 1 / 2
BRID k Branch if Interrupt Disabled if (I == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRIE k Branch if Interrupt Enabled if (I == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRLO k Branch if Lower if (C == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRLT k Branch if Less Than, Signed if (S == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRMI k Branch if Minus if (N == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRNE k Branch if Not Equal if (Z == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRPL k Branch if Plus if (N == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRSH k Branch if Same or Higher if (C == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRTC k Branch if T Bit Cleared if (T == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRTS k Branch if T Bit Set if (T == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRVC k Branch if Overflow Flag isCleared if (V == 0) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRVS k Branch if Overflow Flag is Set if (V == 1) then PC ? PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BSET s Flag Set SREG(s) ? 1 SREG(s) 1 1 1 1
BST Rr, b Bit Store from Register to T T ? Rr(b) T 1 1 1 1
CALL k Call Subroutine PC ? k None 4 / 5(1) 3/ 4(1) 3 /4 N/A
CBI A, b Clear Bit in I/O Register I/O(A, b) ? 0 None 2 1 1 1
CBR Rd,K Clear Bit(s) in Register Rd ? Rd ? (0xFFh - K) Z,N,V,S 1 1 1 1
CLC Clear Carry C ? 0 C 1 1 1 1
CLH Clear Half Carry Flag in SREG H ? 0 H 1 1 1 1
CLI Global Interrupt Disable I ? 0 I 1 1 1 1
CLN Clear Negative Flag N ? 0 N 1 1 1 1
CLR Rd Clear Register Rd ? Rd ? Rd Z,N,V,S 1 1 1 1
CLS Clear Sign Bit S ? 0 S 1 1 1 1
CLT Clear T in SREG T ? 0 T 1 1 1 1
CLV Clear Two’s ComplementOverflow V ? 0 V 1 1 1 1
CLZ Clear Zero Flag Z ? 0 Z 1 1 1 1
COM Rd One’s Complement Rd ? 0xFF - Rd Z,C,N,V,S 1 1 1 1
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1 1 1 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1 1 1 1
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1 1 1 1
CPSE Rd,Rr Compare, skip if Equal if (Rd == Rr) PC ? PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
DEC Rd Decrement Rd ? Rd - 1 Z,N,V,S 1 1 1 1
DES K Data Encryption if (H == 0), R15:R0if (H == 1), R15:R0? ?Encrypt(R15:R0, K)Decrypt(R15:R0, K) N/A 1 / 2 N/A N/A
EICALL Extended Indirect Call to (Z) PC(15:0)PC(21:16)? ?ZEIND None 4(1) 3(1) 3 N/A
EIJMP Extended Indirect Jump to (Z) PC(15:0)PC(21:16)? ?ZEIND None 2 2 2 N/A
ELPM Extended Load Program Memory R0 ? PS(RAMPZ:Z) None 3 3 3 N/A
ELPM Rd, Z Extended Load Program Memory Rd ? PS(RAMPZ:Z) None 3 3 3 N/A
ELPM Rd, Z+ Extended Load Program Memoryand Post-Increment Rd(RAMPZ:Z)? ?PS(RAMPZ:Z)(RAMPZ:Z) + 1 None 3 3 3 N/A
EOR Rd, Rr Exclusive OR Rd ? Rd ? Rr Z,N,V,S 1 1 1 1
FMUL Rd,Rr Fractional MultiplyUnsigned R1:R0 ? Rd x Rr<<1 (UU) Z,C 2 2 2 N/A
FMULS Rd,Rr Fractional Multiply Signed R1:R0 ? Rd x Rr<<1 (SS) Z,C 2 2 2 N/A
FMULSU Rd,Rr Fractional Multiply Signedwith Unsigned R1:R0 ? Rd x Rr<<1 (SU) Z,C 2 2 2 N/A
ICALL Indirect Call to (Z) PC(15:0)PC(21:16)? ?Z 0 None 3 / 4(1) 2 / 3(1) 2 / 3 3
IJMP Indirect Jump to (Z) PC(15:0)PC(21:16)? ?Z 0 None 2 2 2 2
IN Rd, A In From I/O Location Rd ? I/O(A) None 1 1 1 1
INC Rd Increment Rd ? Rd + 1 Z,N,V,S 1 1 1 1
JMP k Jump PC ? k None 3 3 3 N/A
LAC Z, Rd Load and Clear DS(Z)Rd? ?(0xFF – Rd) ? DS(Z)DS(Z) None N/A 2 N/A N/A
LAS Z, Rd Load and Set DS(Z)Rd? ?Rd v DS(Z)DS(Z) None N/A 2 N/A N/A
LAT Z, Rd Load and Toggle DS(Z)Rd? ?Rd ? DS(Z)DS(Z) None N/A 2 N/A N/A
LD Rd, Y Load Indirect Rd ? DS(Y) None 2(1) 2(1)(3) 2(2) 1 / 2
LD Rd, Y+ Load Indirect and Post-Increment RdY? ?DS(Y)Y + 1 None 2(1) 2(1)(3) 2(2) 2 / 3
LD Rd, -Y Load Indirect and Pre-Decrement YRd? ?Y - 1DS(Y) None 2(1) 3(1)(3) 2(2) 2 / 3
LD Rd, Z Load Indirect Rd ? DS(Z) None 2(1) 2(1)(3) 2(2) 1 / 2
LD Rd, Z+ Load Indirect and Post-Increment RdZ? ?DS(Z)Z+1 None 2(1) 2(1)(3) 2(2) 2 / 3
LD Rd, -Z Load Indirect and Pre-Decrement ZRd? ?Z - 1DS(Z) None 2(1) 3(1)(3) 2(2) 2 / 3
LD Rd, X Load Indirect Rd ? DS(X) None 2(1) 2(1)(3) 2(2) 1 / 2
LD Rd, X+ Load Indirect and Post-Increment RdX? ?DS(X)X + 1 None 2(1) 2(1)(3) 2(2) 2 / 3
LD Rd, -X Load Indirect and Pre-Decrement XRd? ?X - 1DS(X) None 2(1) 3(1)(3) 2(2) 2 / 3
LDD Rd, Y+q Load Indirect with Displacement Rd ? DS(Y + q) None 2(1) 3(1)(3) 2(2) N/A
LDD Rd, Z+q Load Indirect with Displacement Rd ? DS(Z + q) None 2(1) 3(1)(3) 2(2) N/A
LDI Rd, K Load Immediate Rd ? K None 1 1 1 1
LDS Rd, k Load Direct from Data Space Rd ? DS(k) None 2(1) 3(1)(3) 3(2) 2
LPM Load Program Memory R0 ? PS(Z) None 3 3 3 N/A
LPM Rd, Z Load Program Memory Rd ? PS(Z) None 3 3 3 N/A
LPM Rd, Z+ Load Program Memory and PostIncrement RdZ? ?PS(Z)Z + 1 None 3 3 3 N/A
LSL Rd Logical Shift Left CRd(n+1)Rd(0)? ? ?Rd(7)Rd(n), n=6...00 Z,C,N,V,H 1 1 1 1
LSR Rd Logical Shift Right CRd(n)Rd(7)? ? ?Rd(0)Rd(n+1), n=0...60 Z,C,N,V 1 1 1 1
MOV Rd, Rr Copy Register Rd ? Rr None 1 1 1 1
MOVW Rd, Rr Copy Register Pair R[d + 1]:Rd ? R[r + 1]:Rr None 1 1 1 N/A
MUL Rd,Rr Multiply Unsigned R1:R0 ? Rd x Rr (UU) Z,C 2 2 2 N/A
MULS Rd,Rr Multiply Signed R1:R0 ? Rd x Rr (SS) Z,C 2 2 2 N/A
MULSU Rd,Rr Multiply Signed withUnsigned R1:R0 ? Rd x Rr (SU) Z,C 2 2 2 N/A
NEG Rd Two’s Complement Rd ? 0x00 - Rd Z,C,N,V,S,H 1 1 1 1
NOP No Operation None 1 1 1 1
OR Rd, Rr Logical OR Rd ? Rd v Rr Z,N,V,S 1 1 1 1
ORI Rd, K Logical OR with Immediate Rd ? Rd v K Z,N,V,S 1 1 1 1
OUT A, Rr Out To I/O Location I/O(A) ? Rr None 1 1 1 1
POP Rd Pop Register from Stack Rd ? STACK None 2 2(1) 2 3
PUSH Rr Push Register on Stack STACK ? Rr None 2 1(1) 1 1
RCALL k Relative Call Subroutine PC ? PC + k + 1 None 3 / 4(1) 2 / 3(1) 2 / 3 3
RET Subroutine Return PC ? STACK None 4 / 5(1) 4 / 5(1) 4 / 5 6
RETI Interrupt Return PC ? STACK I 4 / 5(1) 4 / 5(1) 4 / 5 6
RJMP k Relative Jump PC ? PC + k + 1 None 2 2 2 2
ROL Rd Rotate Left Through Carry tempCRd(n+1)Rd(0)? ? ? ?CRd(7)Rd(n), n=6...0temp Z,C,N,V,H 1 1 1 1
ROR Rd Rotate Right Through Carry tempCRd(n)Rd(7)? ? ? ?CRd(0)Rd(n+1), n=0...6temp Z,C,N,V 1 1 1 1
SBC Rd, Rr Subtract with Carry Rd ? Rd - Rr - C Z,C,N,V,S,H 1 1 1 1
SBCI Rd, K Subtract Immediate withCarry Rd ? Rd - K - C Z,C,N,V,S,H 1 1 1 1
SBI A, b Set Bit in I/O Register I/O(A, b) ? 1 None 2 1 1 1
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) == 0) PC ? PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) == 1) PC ? PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2
SBIW Rd, K Subtract Immediate fromWord R[d + 1]:Rd ? R[d + 1]:Rd - K Z,C,N,V,S 2 2 2 N/A
SBR Rd,K Set Bit(s) in Register Rd ? Rd v K Z,N,V,S 1 1 1 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) == 0) PC ? PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) == 1) PC ? PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
SEC Set Carry C ? 1 C 1 1 1 1
SEH Set Half Carry Flag in SREG H ? 1 H 1 1 1 1
SEI Global Interrupt Enable I ? 1 I 1 1 1 1
SEN Set Negative Flag N ? 1 N 1 1 1 1
SER Rd Set Register Rd ? 0xFF None 1 1 1 1
SES Set Sign Bit S ? 1 S 1 1 1 1
SET Set T in SREG T ? 1 T 1 1 1 1
SEV Set Two’s Complement Overflow V ? 1 V 1 1 1 1
SEZ Set Zero Flag Z ? 1 Z 1 1 1 1
SLEEP Sleep See the power management and sleep description None 1 1 1 1
SPM Store Program Memory PS(RAMPZ:Z) ? R1:R0 None -(4) -(4) -(4) N/A
SPM Z+ Store Program Memory and PostIncrement by 2 PS(RAMPZ:Z)Z? ?R1:R0Z + 2 None N/A - (4) -(4) N/A
ST X, Rr Store Indirect DS(X) ? Rr None 2(1) 1(1) 1(2) 1
ST X+, Rr Store Indirect and Post-Increment DS(X)X? ?RrX + 1 None 2(1) 1(1) 1(2) 1
ST -X, Rr Store Indirect and Pre-Decrement XDS(X)? ?X - 1Rr None 2(1) 2(1) 1(2) 2
ST Y, Rr Store Indirect DS(Y) ? Rr None 2(1) 1(1) 1(2) 1
ST Y+, Rr Store Indirect and Post-Increment DS(Y)Y? ?RrY + 1 None 2(1) 1(1) 1(2) 1
ST -Y, Rr Store Indirect and Pre-Decrement YDS(Y)? ?Y - 1Rr None 2(1) 2(1) 1(2) 2
ST Z, Rr Store Indirect DS(Z) ? Rr None 2(1) 1(1) 1(2) 1
ST Z+, Rr Store Indirect and Post-Increment DS(Z)Z? ?RrZ + 1 None 2(1) 1(1) 1(2) 1
ST -Z, Rr Store Indirect and Pre-Decrement ZDS(Z)? ?Z - 1Rr None 2(1) 2(1) 1(2) 2
STD Y+q, Rr Store Indirect with Displacement DS(Y + q) ? Rr None 2(1) 2(1) 1(2) N/A
STD Z+q,Rr Store Indirect with Displacement DS(Z + q) ? Rr None 2(1) 2(1) 1(2) N/A
STS k, Rr Store Direct to Data Space DS(k) ? Rd None 2(1) 2(1) 2(2) 1
SUB Rd, Rr Subtract without Carry Rd ? Rd - Rr Z,C,N,V,S,H 1 1 1 1
SUBI Rd, K Subtract Immediate Rd ? Rd - K Z,C,N,V,S,H 1 1 1 1
SWAP Rd Swap Nibbles Rd(3..0) ? Rd(7..4) None 1 1 1 1
TST Rd Test for Zero or Minus Rd ? Rd ? Rd Z,N,V,S 1 1 1 1
WDR Watchdog Reset See the Watchdog Controller description None 1 1 1 1
XCH Z, Rd Exchange DS(Z) ? Rd None N/A 2 N/A N/A

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