EternitYjl

EternitYjl

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transientfail

Website and PoC collection for transient execution attacks

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vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

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spectre-attack

Example of using revealed "Spectre" exploit (CVE-2017-5753 and CVE-2017-5715)

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gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

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prospect

ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.

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unicorn

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

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Test-Suite-Transient-Execution

Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly

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spectre-meltdown-checker

Reptar, Downfall, Zenbleed, ZombieLoad, RIDL, Fallout, Foreshadow, Spectre, Meltdown vulnerability/mitigation checker for Linux & BSD

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Security-RISC

Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)

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BOOMv3-SpecShield

SpecShield Transient Execution Attack Mitigation Techniques Implemented on BOOM

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SecureBOOM

Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)

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sonicboom-attacks

SonicBOOM Spectre Attacks

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boom-attacks

Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)

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BOOMv3-eager-delay

Patched version of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. Meltdown and Spectre vulnerabilities

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upec-boom-verification-suite

This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.

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