EngRaff92

APB_SLAVE

APB_SLAVE with open source Full DV environment

ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

RDL_REG_GEN

pyuvm

The UVM written in Python

RISCV_MYTH_SV

Labs from RISCV_MYTH training without TL Verilog but only using SV - COCOTB - YOSYS

yosys-cookbook

User-friendly explanation of Yosys options

activecore

Hardware generation library based on "Kernel IP" (KIP) cores (microarchitectural programmable templates)

apb

APB Logic

apb_gpio

assertion_rerun

Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

cocotb-test

Unit testing for cocotb

common_cells

Common SystemVerilog components

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

EngRaff92_Hackathon

challenges-EngRaff92 forked

Enigma_Machine_ICE40

Enigma Machine Project implemented on Icesugar Ice40 FPGA

ice40-playground

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

mpsoc_example

neoTRNG

:game_die: A Tiny and Platform-Independent True Random Number Generator for any FPGA.

nerv

Naive Educational RISC V processor

opentitan

OpenTitan: Open source silicon root of trust

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-simple

Computer architecture learning environment using FPGAs

riscv-simple-sv

A simple RISC V core for teaching

riscv-tests

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SIMPLE_RISCV

the_verification_adventure

Toast-RV32i

A Pipelined RISC-V RV32I Core in SystemVerilog