EddyChenn / EE457_FIFO_Lab

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EE457_FIFO_Lab

This is EE457_FIFO_Lab of USC; A signle clock 16-location FIFO with 4-bit pointer, so Almost Full and Almost Empty should be carefully designed;

10/4/22 in LA

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Language:VHDL 56.9%Language:Verilog 22.4%Language:Stata 20.7%