EagleStephen

Basys3-VHDL-Basics

This repository has basic examples in VHDL using Basys3 board.

axi_test

master and slave with axi protocol on vhdl

EagleStephen

Config files for my GitHub profile.

Division_VHDL

uart-vhdl

Full-featured AXI UART w/ parameterized TX/RX buffers, baud rate, and data width.

FIFO-VHDL-Simple-Code-

Simple Fifo in VHDL

uart_tx_with_AMBA

This is a very lite AMBA Slave connected to 2 registers and a uart transmitter

vhdl-source

TCL_Script_Modelsim

TCL template duolos for Modelsim

modelsim_compile_simulate

-vlib work , vmap vsim vcom add wave etc..

dice7seg

VHDL code for 7 segement decoder for a dice game

AI_image_generator

This is an ai image generator ran in Jupyter

Arduino

Arduino : Detection Project

vercel

3Dassets

Characters