DuanxiangLiu

SkyPlace

CUDA-Programming-Guide-in-Chinese

This is a Chinese translation of the CUDA programming guide

torch-dct

DCT (discrete cosine transform) functions for pytorch

clash-verge-rev

Continuation of Clash Verge - A Clash Meta GUI based on Tauri (Windows, MacOS, Linux)

thrust

[ARCHIVED] The C++ parallel algorithms library. See https://github.com/NVIDIA/cccl

black-parrot

A Linux-capable RISC-V multicore for and by the world

AMF-Placer

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

ChiPBench

ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms

FloorSet

OpenSTA

GCS-Timer

BlobPlacement

pymoo

NSGA2, NSGA3, R-NSGA3, MOEAD, Genetic Algorithms (GA), Differential Evolution (DE), CMAES, PSO

BayesianOptimization

A Python implementation of global optimization with gaussian processes.

TritonPart

The first version of TritonPart

cuda-samples

Samples for CUDA Developers which demonstrates features in CUDA Toolkit

BasicCUDA

A tutorial for CUDA&PyTorch

lefdef-toolkit

Source code for LEF/DEF

DG-RePlAce

GPU-accelerated RePlAce

Pytorch-Memory-Utils

pytorch memory track code

MacroPlacement

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

3D-Placement

This repository is based on ICCAD contest 2022

2022-ICCAD-Problem-B

Problem B: 3D Placement with D2D Vertical Connections

taskflow

A General-purpose Task-parallel Programming System using Modern C++

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Book-Mathematical-Foundation-of-Reinforcement-Learning

This is the homepage of a new book entitled "Mathematical Foundations of Reinforcement Learning."

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

METIS

METIS - Serial Graph Partitioning and Fill-reducing Matrix Ordering

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more