Dogdive

Dogdive

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Dogdive's starred repositories

Current_Version

Initial Version of the MP120TC 3D printed 6x7cm Technical camera

Stargazers:16Issues:0Issues:0

Cthulhu-Scheme

A primitive bare-metal Scheme for the 65c02

Language:AssemblyLicense:NOASSERTIONStargazers:4Issues:0Issues:0

Sweeter16

A New implementation of Steve Wozniak's Sweet16 Virtual Machine for the 65C02/65C816

Language:AssemblyLicense:CC0-1.0Stargazers:14Issues:0Issues:0

rom4x

*Archived because I am not permitted to make/accept changes for the foreseeable future* Improved Apple //c (ROM 4X) and Apple IIc Plus (ROM 5X) firmware.

Language:AssemblyStargazers:78Issues:0Issues:0

verilog-65C02-microcode

65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface

Language:VerilogStargazers:71Issues:0Issues:0

Kale

An Apple II+ retro computer implemented with FPGA

Language:CLicense:GPL-3.0Stargazers:2Issues:0Issues:0

Apple1-MAX

FPGA Apple1 with some extras for CycloneIV

Language:Propeller SpinLicense:Apache-2.0Stargazers:3Issues:0Issues:0

Apple2plus

Apple 2 plus compatible implementation on an FPGA

Language:SystemVerilogLicense:GPL-3.0Stargazers:6Issues:0Issues:0

Apple_II_vhdl

Apple ][+ implemented in VHDL for FPGAs

Language:VHDLStargazers:6Issues:0Issues:0

AppleFPGA

Apple IIe in FPGA

Language:VerilogStargazers:4Issues:0Issues:0

apple2fpga

port of Stephen A. Edwards apple2fpga to ULX3S

Language:VHDLStargazers:12Issues:0Issues:0

apple-one

An attempt at a small Verilog implementation of the original Apple 1 on an FPGA

Language:VerilogLicense:Apache-2.0Stargazers:130Issues:0Issues:0
Language:VerilogStargazers:32Issues:0Issues:0

PanoLogicG2

Generic repository for Pano Logic G2 experimenting

Stargazers:1Issues:0Issues:0

Panotest

Pano logic g2 test fpga

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Pano_Logic

My things for Pano Logic

Language:CLicense:GPL-3.0Stargazers:2Issues:0Issues:0

pano_logic

Various cores and experiments for Pano Logic Zero Client G1 and G2

Language:VerilogLicense:GPL-3.0Stargazers:4Issues:0Issues:0

Pano-Logic-Zero-Client-G2-FPGA-Demo

Constraints file and Verilog demo code for the Pano Logic Zero Client G2

Language:VerilogLicense:Apache-2.0Stargazers:16Issues:0Issues:0

panologic-g2

Pano Logic G2 Reverse Engineering Project

Language:VerilogLicense:Apache-2.0Stargazers:135Issues:0Issues:0

PanoLogicG2_ReverseEngineering

A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client

Stargazers:33Issues:0Issues:0