Work assignment for the class of Computer Architecture II, that has the objective of simulating data exchange between two computational sets through the use of UARTs (asynchronous serial communication).
Work assignment for the class of Computer Architecture II, that has the objective of simulating data exchange between two computational sets through the use of UARTs (asynchronous serial communication) in a VHDL-made MIPS architecture. The specs of the assignmment are avaliable in the folder Documentation, such as its final report (Portuguese only).
Work assignment for the class of Computer Architecture II, that has the objective of simulating data exchange between two computational sets through the use of UARTs (asynchronous serial communication).