Jerry's repositories
chipyard_jerryhopatch
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chirp
A teaching example of the MEAN stack, by building a simple Twitter clone
chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
chisel3
Chisel 3
clarvi
Clarvi simple RISC-V processor for teaching
CNRV-FPU
Basic floating-point components for RISC-V processors
documents
riscv.github.io
e200_opensource
The Ultra-Low Power RISC Core
first-metro
this will be the place where i place my first metro app.
floating-point-guide
《关于浮点运算:作为程序员都应该了解什么?》
home
为推广RISC-V尽些薄力
JavaGuide
【Java学习+面试指南】 一份涵盖大部分Java程序员所需要掌握的核心知识。
JZSwipeCell
Inspired by MailboxApp (http://mailboxapp.com). A UITableViewCell subclass that makes it easy to add long, short, left and right swiping of content in your table views. Features 4 swipe zones with customizable icons, colors and sizes.
programmer-job-blacklist
:see_no_evil:程序员找工作黑名单,换工作和当技术合伙人需谨慎啊 更新有赞
risc-v-getting-started-guide
The official RISC-V getting started guide
riscv-boom
BOOM: Berkeley Out-of-Order Machine
riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-vector
Vector Acceleration IP core for RISC-V*
rocket-chip
Rocket Chip Generator
rocket-tools
Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
sodar_impl
This is accessory project for the famous UC Berkerly sodar project, which add some form of descriptions and code comments.
stanfordnlp
Official Stanford NLP Python Library for Many Human Languages