Politecnico di Milano - Prof. Fabio Salice - Digital Circuits Design
Final Grade: 30 Cum Laude / 30
The purpose of the project is to implement a hardware module that replicates the functionalities of a pointer dereferencer, commonly found in programming languages such as C.
At a high level of abstraction, the system receives instructions regarding a memory location, the contents of which need to be directed to one of the four available output channels. Instructions about the channel to use and the memory address to access are provided through a serial input bit, while the system outputs, namely the aforementioned channels, provide all the memory word bits in parallel.
The module to be implemented has two primary 1-bit inputs (W and START) and 5 primary outputs. The outputs are as follows: four 8-bit outputs (Z0, Z1, Z2, Z3) and one 1-bit output (DONE). Additionally, the module has a clock signal (CLK), unique to the entire system, and a reset signal (RESET), also unique.
I have designed a sequential component fully specified in VHDL language, programmed using Xilinx's Vivado. The component is modeled as an asynchronous Mealy machine, with its state graph detailed in the documentation. The final outcome is a properly functioning Finite State Machine (FSM) translated into electronic circuitry ready for implementation on a commercial FPGA.