DanialFathpour

OpenFPGA

An Open-source FPGA IP Generator

siliconcompiler

A modular build system for hardware

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

esp-now

A connectionless Wi-Fi communication protocol

painlessMesh

ESP8266 based mesh. This is a mirror copy of https://gitlab.com/painlessMesh/painlessMesh PLEASE ADD COMMENTS, ISSUES and PULL REQUESTS ON GITLAB so that all information is centralized.

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

clear

clear_old

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

zigbee2mqtt

Zigbee 🐝 to MQTT bridge 🌉, get rid of your proprietary Zigbee bridges 🔨

FiraCode

Free monospaced font with programming ligatures

circuitikz

CircuiTikZ TeX/LaTeX package for drawing circuits

justforfun

فقط برای تفریح - داستان یک انقلابی اتفاقی: لینوس توروالدز

awesome-embedded-rust

Curated list of resources for Embedded and Low-level development in the Rust programming language

emb-rust

Embedded Rust example for STM32F4-Discovery board.

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chiselv

A RISC-V Core (RV32I) written in Chisel HDL

microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

pseudos

A little risc-v assembly OS that can run DOOM on a QEMU riscv64 Virt

AwesomeRISC-VResources

It contains a curated list of awesome RISC-V Resources.

ee

EEPROM emulation for stm32.

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

lpic1book

master-thesis

Master thesis GitHub repository. Cheers to public data.

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Physically-Unclonable-Functions-for-Hardware-Security

PUF is a digital Fingerprint used to prevent semi-conductor device designs of a particular company to be stolen, copied or remade by the Foundry or any other company. This project was to analyze which out of Arbiter or Butterfly PUFs work the best for Hardware Security.

spat

A graphical user interface for measuring and performing inter-active analysis of physical unclonable functions (PUFs)

HDLab-FPGA-Development-Board

Open source FPGA development platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

LPN-based_PUF

FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.