This github repository maps the progress made in the ASIC design class under the guidance of Kunal Ghosh(Founder & CEO Inscopix,Inc). The repository progress as the project proceeds and utilizes the specific tool wherever its needed. Repository will also act as a reference to aspirants who aspire to work in semiconductor industry, all the tools used here are open source and all the necessary instructions are provided wherever its needed.
ASIC stands for Application Specific Integrated Chips, as name suggests these chips are hard coded i.e. made for specific purpose and user can't change its functionality/program as incase of FPGA or Gate Array. These chips are are highly optimised when it comes to the three main aspects of a silicon chip i.e. small area, low power consumption & high performance. But all this comes at a cost hence ASIC chips are costly and using this is only viable when chips are manufactured in large number.
The whole process of ASIC design is shown below in the image
Before moving towards the first step of learning the fundamental concepts ASIC design. This section deals with the installation of necessary tools required for the ASIC design.
Knowing Yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications:
Process almost any synthesizable Verilog-2005 design Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc. Built-in formal methods for checking properties and equivalence Mapping to ASIC standard cell libraries (in Liberty File Format) Mapping to Xilinx 7-Series and Lattice iCE40 and ECP5 FPGAs Foundation and/or front-end for custom flows Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base. Yosys also serves as backend for several tools that use formal methods to reason about designs, such as sby for SMT-solver-based formal property checking or mcy for evaluating the quality of testbenches with mutation coverage metrics. Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license)
Steps to Install Yosys
$ git clone https://github.com/YosysHQ/yosys.git
$ cd yosys-master
$ sudo apt install make
$ sudo apt-get install build-essential clang bison flex \
libreadline-dev gawk tcl-dev libffi-dev git \
graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
$ make
$ sudo make install
Knowing Icarus Verilog
ICARUS VERILOG Icarus Verilog is an implementation of the Verilog hardware description language compiler that generates netlists in the desired format (EDIF). It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog, and some extensions.Icarus Verilog is released under the GNU General Public License, Icarus Verilog is free software. Icarus is composed of a Verilog compiler (including a Verilog preprocessor) with support for plug-in backends, and a virtual machine that simulates the design.
Steps to install Verilog
sudo apt-get install iverilog
Knowing GTKWave
### Knowing GTKWave GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.Steps to install GTKWave
sudo apt update<br>
sudo apt install gtkwave
Knowing NGSPICE
ngspice is the open source spice simulator for electric and electronic circuits comprising of JFETs, bipolar and MOS transistors, passive elements like R, L, or C, diodes, transmission lines and other devices, all interconnected in a netlist. Digital circuits are simulated as well, event driven and fast, from single gates to complex circuits. And you may enter the combination of both analog and digital as a mixed-signal circuit. ngspice offers a wealth of device models for active, passive, analog, and digital elements. Model parameters are provided by our collections, by the semiconductor device manufacturers, or from semiconductor foundries. The user can add their circuits as a netlist, and the output is one or more graphs of currents, voltages and other electrical quantities or is saved in a data file.
Steps to install ngspice
Download the tarball from https://sourceforge.net/projects/ngspice/files/ to a local directory and then follow the commands given below :
# Dependency for ngspice:
sudo apt-get install build-essential
sudo apt-get install libxaw7-dev
# ngspice installation:
tar -zxvf ngspice-40.tar.gz
cd ngspice-40
mkdir release
cd release
../configure --with-x --with-readline=yes --disable-debug
make
sudo make install
Knowing Openlane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. It also provides a number of custom scripts for design exploration and optimization. The flow performs all ASIC implementation steps from RTL all the way down to GDSII. Currently, it supports both A and B variants of the sky130 PDK, the C variant of the gf180mcu PDK, and instructions to add support for other (including proprietary) PDKs are documented. OpenLane abstracts the underlying open source utilities, and allows users to configure all their behavior with just a single configuration file.
Steps to install Openlane
Prior to the installation of the OpenLane install the dependencies and packages using the command shown below :
sudo apt-get update
sudo apt-get upgrade
sudo apt install -y build-essential python3 python3-venv python3-pip make git
Docker Installation :
sudo apt install apt-transport-https ca-certificates curl software-properties-common
curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /usr/share/keyrings/docker-archive-keyring.gpg
echo "deb [arch=amd64 signed-by=/usr/share/keyrings/docker-archive-keyring.gpg] https://download.docker.com/linux/ubuntu $(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
sudo apt update
sudo apt install docker-ce docker-ce-cli containerd.io
sudo docker run hello-world
sudo groupadd docker
sudo usermod -aG docker $USER
sudo reboot
# Check for installation
sudo docker run hello-world
Knowing Magic
Magic is an electronic design automation (EDA) layout tool for very-large-scale integration (VLSI) integrated circuit (IC) originally written by John Ousterhout and his graduate students at UC Berkeley. Work began on the project in February 1983. The main difference between Magic and other VLSI design tools is its use of "corner-stitched" geometry, in which all layout is represented as a stack of planes, and each plane consists entirely of "tiles" (rectangles). Magic is primarily famous for writing the scripting interpreter language Tcl.
Steps to install magic
sudo apt-get install m4
sudo apt-get install tcsh
sudo apt-get install csh
sudo apt-get install libx11-dev
sudo apt-get install tcl-dev tk-dev
sudo apt-get install libcairo2-dev
sudo apt-get install mesa-common-dev libglu1-mesa-dev
sudo apt-get install libncurses-dev
git clone https://github.com/RTimothyEdwards/magic
cd magic
./configure
make
sudo make install
Knowing OpenSTA
OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats such as Verilog netlist, Liberty library, SDC timing constraints, SDF delay annotation and SPEF parasitics. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints and print timing reports.
Steps to install OpenSTA Prior to the installation of the OpenSTA install the dependencies using the command shown below :
sudo apt-get install cmake clang gcc tcl swig bison flex
After installing the dependencies use the following command to install OpenSTA:
git clone https://github.com/The-OpenROAD-Project/OpenSTA.git
cd OpenSTA
mkdir build
cd build
cmake ..
make
sudo make install
Summary
Day1 deals with knowing software, that which tool is used for what purpose at which stage of the design flow. Here I learned the meaning of basic terminologies used during synthesis.Introduction
A simulator is a software tool that can be used to check the functionality of a circuit design before it is implemented in hardware. It does this by simulating the behavior of the design in software, using a Hardware Description Language (HDL) such as Verilog or VHDL. RTL design is checked for adherence to the specifications by simulating the design. Simultor looks for the chnages on the input signals. Output of the simulator is a vcd file i.e. value change dump format.
Design is the actual verilog code or set of verilog codes which has the intended functionality to meeet with the required specifications. Design can be of different types like Behavioral, Structural, Data flow model. Here I have started with the behavioral design of a MUX.
Testbench is the setup to apply stimulus(test_vectors) to the design to check its functionality. Here I have uploaded the test bench for the for the MUX design.
Steps to clone the repository
First I made a new directory VSD, follow commands were used
mkdir VSD
cd VSD
mkdir VLSI
In VLSI directory I clonned the following github repository
https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop.git
Following commands were used to clone the github repository
git clone https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop.git
Accessing the files After clonning the github repository here I accessed the content of the repository using the following commands
cd VSD
cd VLSI
cd sky130RTLDesignAndSynthesisWorkshop
cd verilog_files
The verilog_model folder in \wsl.localhost\Ubuntu\home\vsd\VLSI\sky130RTLDesignAndSynthesisWorkshop\my_lib. The verilog_files folder contains all the lab experiment verilog source files and corresponding testbench files needed to simulate the designs.
Demostration of the Icarus Verilog and GTKWave
Demostration of the Icarus Verilog and GTKWave
To run the iverilog command the unbuntu should be in the same directory where verilog log files are presesnt this is done using the following commands
/home/vsd/VLSI/sky130RTLDesignAndSynthesisWorkshop/verilog_files
Now simulation of RTL design and test bench is done using the following commands
iverilog good_mux.v tb_good_mux.v
The above command will compile and check for the syntax errors in both the design and testbench. Upon compiling successfully it will generate an executable file a.out.
Execute the a.out using the command ./a.out , resulting in the generation of a tb_good_mux.vcd file that captures changes in the input and output values. This vcd file is given as the input to the GTKWave to view the wave form. In GTKWave drag and drop the required input and output signals to view the waveform. Since the simulation is done for long amount of time use the zoom to fit option to view the entire waveform.
Commands to execute to view the waveform :
gtkwave tb_good_mux.vcd
Descrpition of Verilog Code
The verilog code can be viewed using the following commands
gedit good_mux.v
The above code opens the verilog code for 2x1 MUX writen in behavioral pattern.
gedit tb_good_mux.v
The above code opens the verilog code for test bench of 2x1 MUX writen in behavioral pattern.
Demostration of the Icarus Verilog and GTKWave
Process of Synthesis i.e RTL(Verilog code to Netlist)
Process of Synthesis i.e RTL(Verilog code to Netlist)
Terminologies
Synthesis- Synthesis is the process that converts RTL into a technology-specific gate-level netlist, optimized for a set of pre-defined constraints.
Netlist- Netlist is the schematic or circuit equivalent of the RTL code. Netlist can be of various type based on its representation. A netlist can have elements like MUX, multiplier, adder, etc or it can be a gate level netlist where the given RTL code is implemented using gates the netlist shows the interconnection between gates. Library- Library is the collection of all the standard cells needed to implement the given RTL logic thriugh a circuit. It consists of gates with various configutations 2,3,4 inputs or with different delay times.
Introduction to the synthesizer
Synthesizer is a tool used to convert the RTL from the netlist. Yosys is one such open source synthesizer. Yosys is provided with both the design and its corresponding .lib file, and its task is to generate the netlist. The netlist generated is a depiction of the input design provided to Yosys, contructed using the standard cells available in the .lib file. To validate the synthesis output, the netlist is verified in a manner analogous to how the RTL design is verified. This involves using the same testbench and stimulus set to confirm that the outcomes obtained from the netlist correspond to those acquired when using the RTL design.
Generating the netlist
Here our synthesizer is Yosys, the following image shows the process and three command needed to generate the netlist using yosys
The below picture describes the RTL design along with the netlist corresponding to it.
Verifying the netlist
Netlist verification is done to cross check whether the given netlist performs exactly in the same as the RTL design. The image shows the pictorial representation of verifying the netlist using the test bench.
Need for slow gates in library
Setup Time- The amount of time the data at the synchronous input must be stable before the active edge of the clock.
Hold Time- The amount of time the data at the synchronous input must be stable after the active edge of the clock.
Note- Both setup and hold time for the flipflops is specified in the librbary.
Invoking yosys
yosys
Reading library
read_liberty /home/full directory where RTL code is present.
Reading Verilog code
read_verilog filename.v
Synthesize command
synth -top filename
Abc command
abc_liberty -lib /home/file directory where library is present
Show command
show
Note- In the coming we will see the
The below image explains why we need slower gates. In the image for proper functioning of the circuit data should reach DFFB well before(setup time) the next clock pulse arrives. And DFFB should hold this value for some amount of time (Hold time) so that it can be carry forward the value to next element of the circuit.
Hence we need fast cells to meet the required performance and we need cells that work slow to meet HOLD.
Introduction to timing library
Introduction to timing.libs
Library Name- Sky130
tt- Stands for typical process
025C- Temparature
1V80- Indicates the voltage
Three important parameters
Process- Variations due to fabrication, due to human error every time it cannot be exactly made same
Voltage- Change in voltage results n change in behaviour of circuit.
Temperature- Semiconductors are highly sensitive to temparature.
Cells- Basic entity used to make a circuit like gates flipflops.
Command for getting library
Library details
Hierarchial vs Float synthesis
Hierarchial vs Float synthesis File showing difference between and gates
Behavioral code of AND gate
Searching two input gate in library
Searching three input gate in library
Verilog Code for multiple module
Multiple module command for synthesis and netlist generation
Multiple module hierarchy
Multiple module netlist
Flattned Library file
Flattned netlist
Submodule AND gate
Various Flop Coding Styles and optimization
Various Flop Coding Styles and optimization Sync reset flipflop code
Simulation
Netlist
Async reset flipflop code
Simulation
Netlist
Sync & Async flipflop code
Interesting Optimisation
Interesting Optimisation
Introduction to optimizations
Introduction to optimizations Combinational Logic Optimisation
- Seqeezing the logic to get the most optimised design
- Optimised Design is better interms of area & Power savings There are two ways to do this
- Constant Propagation
- Boolean Logic optimisation
Constant Propagation
Below constant 0 helped to reduce the circuit. Hence term as constant propagation
Boolean Logic optimisation
Example-1
Example-2
Example-3
Example-4
Example-5 Here there is multiple modules present so we will try to check whether those module are being used or not by using following commands:
yosys:read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib
yosys:read_verilog multiple_module_opt2.v
yosys:synth -top multiple_module_opt2
yosys:abc -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib
yosys:flatten
yosys:opt_clean -purge
yosys:show
module sub_module(input a , input b , output y);
assign y = a & b;
endmodule
module multiple_module_opt2(input a , input b , input c , input d , output y);
wire n1,n2,n3;
sub_module U1 (.a(a) , .b(1'b0) , .y(n1));
sub_module U2 (.a(b), .b(c) , .y(n2));
sub_module U3 (.a(n2), .b(d) , .y(n3));
sub_module U4 (.a(n3), .b(n1) , .y(y));
endmodule
Before Flatten
After Flatten
Example -6
module sub_module1(input a , input b , output y);
assign y = a & b;
endmodule
module sub_module2(input a , input b , output y);
assign y = a^b;
endmodule
module multiple_module_opt(input a , input b , input c , input d , output y);
wire n1,n2,n3;
sub_module1 U1 (.a(a) , .b(1'b1) , .y(n1));
sub_module2 U2 (.a(n1), .b(1'b0) , .y(n2));
sub_module2 U3 (.a(b), .b(d) , .y(n3));
assign y = c | (b & n1);
endmodule
Sequential Logic optimizations
- Sequential logic optimisations(basic)
- Advanced 2.1 State Optimisation 2.2 Retiming 2.3 Sequential Logic Clonning(Floor plan aware synthesis) State Optimisation Below figure show the concept of Sequential Constant
Clonning- Done when doing a physical aware synthesis
Below image shows concept of clonning
When distance between A to B & A to C is very large & we have positive slack for A, we introduce more than one unit of A, this reduces the timing delay caused due to large distance.
Retiming
Below image shows the concept of retiming. Assumption clock to Q delay & setup time zero. Effectively we will be able to clock at 200Mhz. After retiming is done circuit can be clocked at 250Mhz, making it faster.
Example-1
Example-2
Example-3
Example-4
Example-5
Sequential optimisation of unused output
Sequential optimisation of unused output Counter
Updated Counter
GLS, Synthesis-Simulation mismatch and blocking,nonblocking statements
GLS, Synthesis-Simulation mismatch and blocking/nonblocking statements
What is GLS- Gate Level Simulation?
GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.
Why GLS?
We perform this to verify logical correctness of the design after synthesizing it. Also ensuring the timing of the design is met.
Below picture gives an insight of the procedure. Here while using iverilog, we also include gate level verilog models to generate GLS simulation.
Synthesis Simulation Mismatch
Synthesis Simulation Mismatch
There are three main reasons for Synthesis Simulation Mismatch:
- Missing sensitivity list in always block
- Blocking vs Non-Blocking Assignments
- Non standard Verilog coding
Missing sensitivity list in always block:
If the consider - Example-2, we can see the only sel is mentioned in the sensitivity list. During the simulation, the waveforms will resemble a latched output but the simulation of netlist will not infer this as the synthesizer will only look at the statements with in the procedural block and not the sensitivity list.
As the synthesizer doen't look for sensitivity list and it looks only for the statements in procedural block, it infers correct circuit and if we simulate the netlist code, there will be a synthesis simulation mismatch.
To avoid the synthesis and simulation mismatch. It is very important to check the behaviour of the circuit first and then match it with the expected output seen in simulation and make sure there are no synthesis and simulation mismatches. This is why we use GLS.
Blocking vs Non-Blocking Assignments:
Blocking statements execute the statemetns in the order they are written inside the always block. Non-Blocking statements execute all the RHS and once always block is entered, the values are assigned to LHS. This will give mismatch as sometimes, improper use of blocking statements can create latches. Get to see at Example4
Labs on GLS and Synthesis-Simulation Mismatch
Labs on GLS and Synthesis-Simulation Mismatch
Example-1
There is no mismatch in this example as the netlist simulation and rtl simulation waveform are similar only
module ternary_operator_mux (input i0 , input i1 , input sel , output y);
assign y = sel?i1:i0;
endmodule
Simulation
Synthesis
Netlist Simulation
Command for netlist verification
Example-2
module bad_mux (input i0 , input i1 , input sel , output reg y);
always @ (sel)
begin
if(sel)
y <= i1;
else
y <= i0;
end
endmodule
Simulation
Synthesis
Netlist Simulation
Mismatch
Here the first image is showing mismatch because waveform was only changing only when select was changing where as in the second one it is corrected by the synthesizer.
Command to get netlist
Example-3
module good_mux (input i0 , input i1 , input sel , output reg y);
always @ (*)
begin
if(sel)
y <= i1;
else
y <= i0;
end
endmodule
Simulation
Synthesis
Netlist Simulation
Labs on synth-sim mismatch for blocking statement
Labs on synth-sim mismatch for blocking statement
Here in the below example the output is depending on the past value of x which is dependednt on a and b and it appears like a flop.
module blocking_caveat (input a , input b , input c, output reg d);
reg x;
always @ (*)
begin
d = x & c;
x = a | b;
end
endmodule
Simulation
Synthesis
Cell Stats
Signal Info
Netlist Verification
If & Case constructs
If & Case constructs
The construct if is mainly used to create priority logic. In a nested if else construct, the conditions are given priority from top to bottom. Only if the condition is satisfied, if statement is executed and the compiler comes out of the block. If condition fails, it checks for next condition and so on as shown below. Syntx of If is shown below
if (<condition 1>)
begin
-----------
-----------
end
else if (<condition 2>)
begin
-----------
-----------
end
else if (<condition 3>)
.
.
.
Dangers due to If
If use a bad coding style i.e, using incomplete if else constructs will infer a latch. We definetly don't require an unwanted latch in a combinational circuit. When an incomplete construct is used, if all the conditions are failed, the input is latched to the output and hence we don't get desired output unless we need a latch. The below image shows dangers with warning in red
Case Construct
In case construct, the execution checks for all the case statements and whichever satisfies the statement, that particular statement is executed.If there is no match, the default statement is executed. But here unlike if construct, the execution doesn't stop once statement is satisfied, but it continues further.
Below snippet show the syntax for case statement
case(statement)
case1: begin
--------
--------
end
case2: begin
--------
--------
end
default:
endcase
Caveats in case occurs due to two primary reasons
- Incomplete case The below image show the code and how a latch is formed in the case statement. Warning are shown in red colour.
Solution- Introducing a default in the code eliminates the problem of latch formation at hardware level.The snippet for which is shown below
- Partial assignments The below image shows the error occured due to partial assingment. Due to this hardware generates some random error. Example of this is discussed in further section.
Lab incomplete if case
Lab incomplete if case
Example-1
The below image shows the practical example where latch is formed due to incomplete if code used.
The below image show the image of latch at hardware level. Whenever io is low y is latching at some value.
The below image show the latch used by the synthesizer to implement the circuit.
The image shows presence of latch in the netlist
The above images shows what an incomplete if state does to the circuit at various levels
Example-2
The below code is equivalent to two 2:1 mux with i0 and i2 as select lines with i1 and i3 as inputs respectively. Here as well, the output is connected back to input in the form of a latch with an enable input of OR of i0 and i2.
The below image shows when i1 and i2 are low the circuit will act as a latch.
The below image shows that the synthesizer used a latch to implement the code at the hardware level.
Below image shows latch present in the netlist.
Lab-Incomplete overlapping case
Lab-Incomplete overlapping case
Example-1
This is an example of incomplete case where other two combinations 10 and 11 were not included. This will infer a latch for the multiplexer and connect i2 and i3 with the output.
Below is the code for the same.
Below show the gtkwave where latch can be observed for (1,0) & (1,1) it's forming the latch. This can be observed between 2ns to 4ns.
The cell stats show the presence of latch in hardware implementation.
Presence of netlist is obserevd in the netlist as well.
Example-2 The below code is equivalent to two 2:1 mux with i0 and i2 as select lines with i1 and i3 as inputs respectively. Here as well, the output is connected back to input in the form of a latch with an enable input of OR of i0 and i2.
Code snippet is given below
Below image of GTKWave show the proper working of case statement by using default statement
Cell stats shows elimination of latch from hardware
Same is reflected in the netlist as well.
Example-3
In the below example, y is present in all the case statements and it had particular outut for all cases. There no latch is inferred in case of y. When it comes to x, it is not assigned for the input 01, therefore a latch is inferred here.
Code snippet is given below
GTKWave show output for both x and y.
Cell stats shows inclusion of latch because of x.
Netlist shows infered latch at output x.
Example-4 Bad Mux Contruct
GTKwave simulation
Cell stats
Netlist
Netlist Simulation
As we can see from the simulation wave form and difference in netlist waveform here the invalid case is getting fixed by the tool which we should avoid to do so in the code
For loop & For Generate
-
For loop is always used inside always block
-
For loop used for evaluating expressions
-
For loop is not used for instantiating Hard Ware multiple times
-
Generate For loop is always used outside always block,
-
Generate For loop is used when we need a code snippet multiple time i.e. used for instatiating Hard Ware.
For loop can be used to generate larger circuits like 256:1 multiplexer or 1-256 demultiplexer where the coding style of smaller mux is not feesible and can have human errors since we would need to include huge number of combinations.
FOR Generate can be used to instantiate any number of sub modules with in a top module. For example, if we need a 32 bit ripple carry adder, instead of instantiating 32 full adders, we can write a generate for loop and connect the full adders appropriately.
Lab- For and For Generate
Lab- For and For Generate Example-1- Mux using generate
Code Snippet
GTKwave output
Netlist
Netlist simulation
Example-2-Demux using case & generate Code snippet
Demux Case RTL simulation
Demux generate RTL simulation
Demux Case Netlist
Demux Generate Netlist
Demux case Netlist Simulation
Demux generated Netlist simulation
Conclusion- Whenever a big mux/demux is needed to be implemented "for" loop is very handy. Making larger mux using case statement is a tedious task, as the code length increases while this is not the case with for generate method.
Example-4 Ripple Carry Adder
In this Ripple carry adder example, unlike instantiating fulladder for 8 times, generate for loop is used to instantiate the fulladder for 7 times and only for first full adder, it is instantiated seperately. Using the same code, just by changing bus sizes and condition of for loop, we can design any required size of ripple carry adder.
Code snippet
Simulation
Introduction to RISC-V
Introduction to RISC-V
RISC stands for Reduced Instruction Set computer. RISC has small number of instructions. RISC-V is an open source ISA(Instruction Set Architeture).
Why does a computer needs a RISC or CISC ISA?
Any computer program or software inorder to work on a computer hardware needs to communicate to the layout(chip present on system). Accomplishment of which requires a process to be followed. First the high level language program is converted to assembly level program(which follows a particular architecture RISC-V in this case). After which it's converted to machine level program for computer to understand.For communication between architeture to layout there is need for a interface, called HDL(Hardware Description Language).
Below image show the whole process of program or application execution.
Applications to Hardware
Applications to Hardware
Inorder to run any application on the computer system. Below process needs to be followed.
The assembly language program is dependent on the processor and its architecture. Every architeture has its own assembly language program. Converting assembly language program to machine level program is done using a specific process, which is elaborated in the flowchart below.
Detailed description of workshop
Word Of Thanks
I would like to thanks Mr. Kunal Ghosh(Founder & CEO VLSI System Design), for guiding me and providing me quality content to know about the chip design flow.
References
- https://www.vsdiat.com/
- Alwin Shaju Colleague at IIIT Bangalore
- Emil Jayanth Lal, Colleague at IIIT Bangalore
- Sushma-Ravindra, Colleague at IIIT Bangalore
- Madhav Rao, Faculty IIIT Bangalore
- Nandita Rao, Faculty IIIT Bangalore
- https://www.idc-online.com/
- Prof Indranail Sengupta, Dept of Computer Science IIT Kharagpur.