DBees

.github

advanced-riscv-verification-methodologies

Advanced Verification Methodologies for RISC-V and related IP

arc_prez

Kaggle Talk on teh Advanced Reasoning Corpus Competition

core-v-cores

CORE-V Family of RISC-V Cores

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

core-v-mcu-devkit

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

core-v-sdk

core-v-sw

Main Repo for the OpenHW Group Software Task Group

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-fake

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P

cva6-sdk-fake

This repo is for experimenting with organization level project boards

cva6-verif-fake

This repo is for experimenting with organization wide project boards

cve2

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

marketing

openhwgroup.org

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.