CrossingX / LDCLD

Laboratory of Digital Circuits and Logical Design, SYSU

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

This repository is not active

About

Laboratory of Digital Circuits and Logical Design, SYSU


Languages

Language:Tcl 46.2%Language:Verilog 19.2%Language:Coq 13.3%Language:JavaScript 9.0%Language:VHDL 6.3%Language:Shell 2.9%Language:Stata 1.4%Language:Forth 1.2%Language:Batchfile 0.5%Language:Pascal 0.2%