Crosshairs

convolution-visualizer

Convolution visualizations

barstools

Useful utilities for BAR projects

berkeley-hardfloat

capstone

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-testers

Provides various testers for chisel users

chisel3

Chisel 3: A Modern Hardware Design Language

emacs

Mirror of GNU Emacs

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

firrtl

Flexible Intermediate Representation for RTL

firrtl-interpreter

A scala based simulator for circuits described by a LoFirrtl file

gemmini

Berkeley's Systolic Array Generator

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

krb5

mirror of MIT krb5 repository

learngit

opensbi

RISC-V Open Source Supervisor Binary Interface

openssl

TLS/SSL and crypto library

plsi-mdf

Macro description format

qemu

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-openocd

Fork of OpenOCD that has RISC-V support

riscv-tests

rocket-chip

Rocket Chip Generator

sifive-blocks

Common RTL blocks used in SiFive's projects

SLOF

Mirror of git.qemu.org/SLOF.git

testchipip

treadle

Chisel/Firrtl execution engine

u-boot

Mirror of git.qemu.org/u-boot.git