Cra2yPierr0t

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cpu-dev

Cra2yPierr0t's repositories

risc-v

RISC-VのCPU作った

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stm32_acc

SPIで制御出来るアクセラレータ

Language:SystemVerilog400

cprv32g

まともなRISC-V CPU

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cpu_pipeline

5段パイプラインのRISC-V CPU

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Cra2yPierr0t.github.io

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I_think_it_will_be_Drone

ドローン作るよ

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caravel_walkthrough_uart

caravel walkthrough for beginners

Language:VerilogApache-2.01 20

cordic

sinを100倍して8bitで即座に計算してくれるやつ

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nand2tetris

O'Reilly コンピュータシステムの理論と実装

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TOY_TPU

取り敢えず動くTPU

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bashcms2

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bashcms2_contents

000

caravel_user_project

https://caravel-user-project.readthedocs.io

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cprv64g_v1

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CUDA

000

demodon

Your self-hosted, globally interconnected microblogging community

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ENC28J60

ENC28J60 FPGAドライバ

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INTERNET_SAKEBI

Hardware Electronic Public Notice System

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KotoamatsuV

⛩

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OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language:VerilogApache-2.0010

riscv-emu

ゆるふわRust製のRISC-Vエミュレータ

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sky130_sram_test

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sscs-ose-code-a-chip.github.io

IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE) - “Code-a-Chip” Travel Grant Awards at ISSCC'23

Apache-2.0000

translated-content

The source repository of all translated content for MDN Web Docs

NOASSERTION000

vcc

risc-v veryvery small c compiler for me

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Vthernet

MAC for Caravel

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Vthernet-SoC

picoRV and Ethernet SoC

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Z16_assembler

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Z16_emulator

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Z16_site

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