Coloquinte / locked-tapeout

Logic locking of a design build on TinyTapeout

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Locking a design using Moosic and TinyTapeout

My Image

Logic locking is a way to secure silicon chips against supply chain attacks. We wrote a Yosys plugin, Moosic, to apply logic locking solutions easily using a fully open source toolchain.

This is a showcase design to show how to apply logic locking on a simple example. It uses TinyTapeout to go all the way to a silicon chip! Have a look at the blog post on the YosysHQ blog for more information.

About

Logic locking of a design build on TinyTapeout

License:Apache License 2.0


Languages

Language:Verilog 52.6%Language:Tcl 23.4%Language:Python 13.6%Language:Makefile 10.4%