Dyxn's repositories
verilog_parser
To look neat, Convert verilog into metadata.
magma
magma circuits
myhdl
The MyHDL development repository
netlist_parser.py
A Python based netlist parser, including Verilog and SPICE
ply
Python Lex-Yacc
PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
pyslang
Python bindings for slang, a library for compiling SystemVerilog
SpaceStreet
First Rep.
sveditor-ref-designs
Reference designs for use in SVEditor benchmarking
systemrdl-compiler
SystemRDL 2.0 language compiler front-end
uvm-python
UVM 1.2 port to Python
tvip-axi
AMBA AXI VIP
veripy
VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation, embedded python, IO spec flow, memory wrapper generation, various code generation plugins and configurable code generation. The VeriPy Wiki has more the detailed documentation.
XiangShan
Open-source high-performance RISC-V processor