              UUUUUUU
                UUU
                 UU
            UUUUUUUUUUUU      UUUUUUUUUU    UUUUU  UUUUU
           UUU   UU   UUU       U      UU    U        U
          UUU    UU    UUU      U       U    U        U
         UUU     UU     UUU     U      U     U        U
         UUU     UU     UUU     U     U      U        U
         UUU     UU     UUU     UUUUUU       U        U
          UU     UU    UUU      U       IOT  U        U
          UUU    UU   UUU       U            U        U
           UUUUU UU UUUU        U     AI     U        U
              UUUUUUUU          U            UU      UU
                UUU    RISC-V   U      Chip   UU    UU
               UUUUU          UUUUUUU          UUUUUU


Designed by Wusystem Group @ ICT, the SoC is an IoT AI chip, including two RISC-V cores and an NPU core, supporting ANN and certain RNN graphs.

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Language:Verilog 53.7%Language:C 16.7%Language:SystemVerilog 14.8%Language:VHDL 3.7%Language:Objective-C 2.8%Language:C++ 2.5%Language:Coq 1.5%Language:Python 1.0%Language:Shell 1.0%Language:Assembly 0.8%Language:Tcl 0.6%Language:CMake 0.2%Language:Perl 0.2%Language:JavaScript 0.1%Language:Makefile 0.1%Language:MATLAB 0.1%Language:Stata 0.1%Language:PHP 0.0%Language:1C Enterprise 0.0%Language:Pascal 0.0%Language:Batchfile 0.0%