Cerebras / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

open-register-design-tool

Ordt is a tool for automation of IC register definition and documentation. It currently supports 2 input formats:

1. SystemRDL - a stardard register description format released by Accellera.org
2. JSpec - a register description format used within Juniper Networks

The tool can generate several outputs from SystemRDL or JSpec, including:

• SystemVerilog/Verilog RTL code description of registers
• UVM model of the registers
• C++ and python models of the registers
• XML and text file register descriptions
• SystemRDL and JSpec (conversion)

Easiest way to get started with ordt is to download a runnable jar from the release area.
Ordt documentation can be found here.